Gallium arsenide (GaAs) technology is advancing rapidly in research laboratories, but has been slow to gain acceptance in commercial applications. Two factors contribute to the reluctance of system designers to incorporate GaAs components in their products: the difficulties of interfacing GaAs components with the silicon bipolar circuitry presently in widespread use, and the limited range of integrated circuit components presently available in GaAs.
The difficulties of interfacing GaAs components with silicon bipolar circuitry stem from the different logic voltage levels required by the different integrated circuit families. Emitter Coupled Logic (ECL), for example, is a high-speed bipolar technology which typically operates at a reference, or common mode level of -1.29 or -1.33 volts and has output swings of 500 millivolts above and below this level. Three-Diode Buffered FET Logic (BFL), one of the GaAs logic families, operates at a reference level of -0.5 volts and has output swings of 1 volt above and below this level.
The translation of logic signals from one such logic family to the other is complicated by the different temperature-response characteristics of the two materials. The reverse saturation current of a silicon diode junction, for example, doubles for every 10.degree. C. rise in temperature. The forward voltage drop across a silicon junction drops 20 millivolts over the same range. Compensation for these temperature related effects is comparatively easy in a wholly silicon based system, since all the circuitry behaves similarly. When a GaAs circuit is interfaced through a translator circuit with a silicon circuit, however, the temperature drift of the silicon generated logic levels will not match the temperature drift of the GaAs logic levels. The translated silicon levels can thus drift away from the desired GaAs levels, causing the system performance to become marginal. Accordingly, proper temperature stabilization of silicon to GaAs translator circuits is an obstacle that must be overcome before GaAs components can enjoy widespread commercial acceptance.
The second factor slowing commercial acceptance of GaAs technology is the limited range of GaAs integrated circuits presently available. This limited range of components can be traced, in part, to the inherent difficulties of implementing certain circuit topologies satisfactorily in GaAs. Differential amplifiers, for example, have been widely used in the silicon integrated circuitry art as building blocks in components such as latches, shift registers and digital-to-analog converters. Optimization of such circuits in GaAs, however, is made difficult by the many problems inherent in GaAs technology which are not present with silicon. Some of these problems include: the inherently low gain of GaAs transistors, the difficulties of fabricating large value resistors and high impedance current sources, the poor matching of adjacent GaAs components, the wide process variations in the pinch-off voltage of GaAs field effect transistors (GaAsFETs) and the dependence of GaAsFET drain currents on their drain to source voltages. Such factors make any symmetrical circuit topology, such as the differential amplifier, difficult to implement in GaAs. Consequently, GaAs circuits which rely on symmetrical topologies, such as logic families that use phase matched differential inputs or outputs, are unavailable.
In response to the interfacing problem, many designers have proposed circuits for translating bipolar ECL logic signals to gallium arsenide compatible levels. One such circuit is shown in FIG. 1. A reference voltage, corresponding to the common mode level of an input ECL signal, is generated by the forward voltage drop across a diode string and is applied to the source of an input GaAsFET. As the input signal swings around the reference voltage, the input GaAsFET will alternately turn on and off, providing an inverted, amplified output signal on its drain. This signal is applied to the gate of a second GaAsFET and serves to turn it on and off. The output voltage on the source of the second GaAsFET is dropped by a second diode string to the desired output voltage level, at which point it is connected to the GaAs circuit being driven.
Circuits such as this, which rely on diodes as reference voltage sources, are highly dependent on a precise ambient temperature for proper operation. In FIG. 1, for example, the voltage at the reference node of the input GaAsFET and the voltage dropped by the output diode string will both be functions of temperature. Such circuits also suffer from the drawback that the diode-established reference voltages will vary with changes in forward current and are subject to process induced variations. Lastly, the required reference voltage must be a multiple of the nominal diode voltage drop. Such fortuitous situations are uncommon and are difficult to force.
An input translator circuit used by Honeywell is discussed in the "IEEE Journal of Solid State Circuits," Vol. SC-19, No. 1, February 1984, page 10. The Honeywell circuit uses a reference voltage which is set by the ratio of the component GaAsFET gate widths. Such a scheme is highly dependent on the pinch-off voltages of the GaAsFETs used. These pinch-off voltages are again functions of ambient temperature, changing at the rate of -1 millivolt per .degree.C., and are further subject to process induced variations of up to 600 millivolts.
An input circuit for Capacitively Coupled Logic (CCL) developed by Bell Telephone Manufacturing Company, Antwerp, Belgium, is disclosed in the "IEEE Journal of Solid State Circuits," Vol. SC-18, No. 3, June 1983, page 359. The amplifier uses a pair of GaAsFETs in a nominally differential configuration. Both of the inputs, however, are capacitively coupled by back-biased diodes. The text of the article indicates that one of the inputs can be used as a reference node and tied to the drain voltage supply. The use of a DC voltage on a capacitively coupled input node, as taught by the reference, causes one of the inputs of the nominally differential pair to float. The differential feature is thus disabled and the circuit operates as a single-ended amplifier. Furthermore, if the circuit were modified to enable differential operation, the outputs would not switch symmetrically about a center, common mode voltage. The absence of a symmetrical output swing, however, does not affect operation of the circuit, as described, because only a single output is used.
An input level translator circuit used by GigaBit Logic is discussed in the "IEEE Technical Digest" from the 1984 GaAs IC Symposium, page 11. An external temperature compensation circuit designed for use with the GigaBit's translator circuit is shown in "Applications Brief 1: Power Supply Requirements for GigaBit's 10G Picobit Logic Family."
The GigaBit level translator is built about an inverting GaAsFET stage. The circuit's switching threshold voltage is set by the ratio of the inverting GaAsFET's gate width to the gate width of a pull-up GaAsFET. The input ECL signal is voltage shifted to be centered about the circuit's switching theshold.
The level shifting of the ECL input signal down to the circuit's switching threshold is effected by a string of series diodes between the ECL input and the gate of the inverting GaAsFET. The voltage drop provided by this series diode string may be varied slightly by varying the forward current passing through the diodes. This forward current is varied by changing a trim voltage that biases the diodes. The trim voltage is provided by a comparator circuit that compares an externally generated ECL reference voltage with an externally generated GaAs reference voltage.
The GigaBit Applications Brief indicates that the temperature compensation circuit is only effective over a 15.degree. C. temperature range. The circuit is not compensated for process variations in the widths of the inverting and pull-up GaAsFET gates. Nor is the circuit compensated for process variations in the voltage dropping diodes. Finally, the trim voltage that "tweaks" the level translating circuit is externally generated and may not have the same temperature or process characteristics as the ECL and GaAs circuits with which the translator is being used.
In sum, the prior art discloses no fully-compensated or self-compensated GaAs translator circuits. Furthermore, all translator circuits currently being used provide poor temperature stability and are dependent on critical manufacturing and processing tolerances. Lastly, the prior art does not disclose any compensated GaAs differential voltage amplifiers.